Plastic dual-in-line packages (DIPs) have been used extensively to house integrated circuits in which lead frames, supported by their edges, are supported in a mold cavity. The plastic is injected around the lead frames, with the ends of the leads extending laterally from the package. The package is provided with a central cavity into which an integrated circuit (IC) is mounted. The integrated circuit is typically wire bonded to contact pads at the ends of the traces which extend into the central cavity of the package and the package is then sealed by a cover. Thereafter, the leads are bent orthogonal to the plane of the package such that their ends define pins which extend at right angles to the package. While it is possible to have pins which completely surround the edge of this type of plastic package, it is not possible by this technique to provide an inwardly extending array of pins because the lead frames are supported by their edges during the molding process.
For very large scale integrated circuits (VLSICs) it is important that the number of leads be increased and, for this purpose, it is desirable to have an array of pins which extend orthogonal to the package and which are arranged inwardly either in concentric rings or rows to provide for double or triple the numbers of pins that could be provided by bent leads at the sides of the package. Thus, the conventional stamped lead frame approach cannot produce high pin count arrays because the lead frame is supported in the mold cavity at its edges.
In the past, in order to provide a pin grid array chip carrier, a ceramic package is provided in which a first level of tungsten leads or traces is patterned onto a ceramic base, with the exterior ends of the traces providing bonding pads to which are attached orthogonal copper alloy leads which are brazed to the bonding pads to form pins. An interior ring or row of leads is provided by overlying the ceramic base with another ceramic layer and patterning another layer of traces onto this layer, again with the traces having bonding pads at their ends. These ends lie inward of the outer ring of the bonding pads on the first layer. Orthogonal leads are then brazed or soldered to these bonding pads to provide the pin grid array. What will be appreciated is that not only are the pins not formed by a simple bending process but also there is a multilayer trace pattern in the ceramic package which is undesirable from the point of view that the bonding pads provided for the wire bonding of the chip are at different levels within the package. Moreover the brazed joint has an unpredictable path resistance which is undesirable.
By way of further background, glass epoxy pin grid array packages have been provided in which printed circuit boards are substituted for the layers of the ceramic package and in which round leads are soldered to the board to provide orthogonal pins, as opposed to the brazing in the ceramic package case. It should be noted in the glass epoxy version of the pin grid array chip carrier the circuit boards have a relatively thin two or three ounce copper trace which has been etched out of copper laminated to the glass epoxy substrate, with the thinness of the trace resulting in relatively high path resistance. Moreover, it should be noted that there is no lead frame in either the glass epoxy or ceramic versions.
It will be appreciated that what is desired is not a conventional dual-in-line package which has two rows of leads projecting from it at right angles to the plane of mounting to the chip, but rather what is desired is a pin grid array which can have as many as four or more concentric rings of pins.
The basic disadvantage to ceramic packaging is that it is expensive and that there are limitations in the control of tolerances because as larger packages are provided they are more and more difficult to fabricate. Also what occurs when providing ceramic packages is that with more and more pins, one cannot achieve a narrow enough tungsten lead without the path rsistance becoming so great that the integrated circuit will not function in the ceramic package provided, thus necessitating multiple layers.
Also, ceramic has a high dielectric constant, which is poor for two reasons. First, when using ceramic it becomes important to minimize the interconnection path length in the high dielectric constant media where the delay difference between it and a lower dielectric constant material can be a significant part of the delay in the circuit element. Emitter coupled logic (ECL) circuits with propagation delays of less than 1 ns are now available. If all interconnections were in alumina ceramic, the delay contribution of six inches of stripline interconnection would be a prohibitive 1.6 ns. If the same interconnection is provided in epoxy glass printed wiring the delay would still be a prohibitive 1.1 ns. Thus, the savings of one-half a circuit delay can be significant to some applications.
Secondly, due to the high dielectric constant of ceramic, the interlead capacitance is high, which results in low speed operation and considerable cross-talk problems.
From the manufacturing point of view, with respect to the conventional injection molding of dual-in-line packages, it will be appreciated that the leads are supported from opposing sides prior to molding. After the package has been molded the leads are bent down perpendicular to the package. However, in a pin grid array, more than two rows of pins or an inner ring of pins is required, which means that lead frames cannot be provided in the flat prior to the molding because the pins would be laying over one another.
In the prior art there are a number of techniques utilized to interconnect an integrated circuit that is already packaged. As such, the total package includes an intermediate connector which is used with an already packaged integrated circuit. These packaging techniques are cumbersome and expensive, and are used to adapt an already packaged die to a particualr pin configuration. One prior art technique is illustrated in U.S. Pat. No. 3,789,341 in which a plastic frame is used to encapsulate the leads. It will be appreciated that in this patent leads are bonded to a carrier to which the chip has already been attached and wire bonded. Here the integrated circuit is already bonded to a substrate and the interconnection means is thereafter provided. It will also be appreciated that the device in this patent is a dual-in-line device in which the leads do not come out on all four sides of the package.
With reference to U.S. Pat. No. 3,892,312, this particular patent refers to a one piece plastic molded carrier for a dual-in-line integrated circuit package or module which is again a packaging means for a device that has already been mounted. Moreover, this patent also refers to a dual-in-line device and not one which has leads perpendicular to the package on all four sides. Additionally, multiple rows are not taught in this patent. It should be noted that one of the principal objects of the above patent is to provide a dual-in-line package carrier in which the integrated circuit module may be inserted and held without imposing any such pressure or stress upon the leads thereof as might damage or completely destroy the operative integrity of the module. This means that an interconnection device is provided which includes a makeable and breakable interconnection between the module and the package. In essence, what is provided in this patent is a chip carrier which in turn is socketed or mounted to a board so that a second interconnection device is interposed. It will also be appreciated from the above two patents that the leads for the dual-in-line package are bent after manufacture into a position normal to the mounting plane.
Reference is also made to U.S. Pat. No. 4,195,193, in which the package described refers to a plastic chip carrier. Again in this patent the leads are bent in a position normal to the seating plane after the molding of the package. Additionally, only one layer and one row can be provided around the perimeter of the package due to the fact that the leads all exit the package at the side. While there are leads on all four sides, only one ring of pins can be provided. It will be appreciated that the package of this patent is intended to be a surface mount package, which is to say that the leads are not left at right angles to the package but rather are curled around so that they can be attached directly to the surface of the board. This precludes the use of this package where pins are required to project into plated thru-holes in a printed circuit board or to pass into a conventional IC socket. In leadless surface mount packaging, pads must be placed around the perimeter of the package which means that as the package pin count increases, the leadless package must increase in circumference to accommodate the increase in leads. This is in contradistinction to the pin grid array package which requires holes in a circuit board to which it is soldered. However, the major distinction is that in a pin grid package the rows can be increased in a pin grid array moving inwardly from the periphery of the package so that more input-output (IO) terminals or leads can be provided for a smaller surface area. Another problem with surface mount devices is the differential in thermal coefficient of expansion between the surface mounted package and the board. Because of the direct soldering of the contact pad to pads on the printed circuit board, considerable stress on these joints can result.
Other patents relating to lead frames and plastic encapsulation include U.S. Pat. Nos. 3,391,382, 3,652,974, 3,678,385, 3,930,115, 3,963,315, 4,026,412, 4,144,648, 4,252,864, 4,329,642, 4,358,173, and 4,387,388. In all of these additional patents their fabrication presumes lead frames which are edge supported as opposed to the center supported method of manufacture described hereinafter.